According to the study by the inventors of the present invention, in a conventional disk array apparatus, there is a technique for adopting a redundant configuration between an I/O processing controller having a cache memory and an upper apparatus considering a case that a failure occurs in the cache memory. When a failure occurs at a part of the cache memory even in the redundant configuration, the I/O processing controller having the cache memory where the failure has occurred is closed and a processing is taken over to an I/O processing controller of another system where an I/O processing can be continued. Here, regarding a disk array apparatus with such a redundant configuration, techniques disclosed in Japanese Patent Application Laid-Open Publication No. 2005-174178 (Patent Document 1), Japanese Patent Application Laid-Open Publication No. 2006-92120 (Patent Document 2) are exemplified.
Meanwhile, in the technique of the disk array apparatus described above, since the I/O processing controller having the cache memory where the failure has occurred is closed to take over the processing to the I/O processing controller of another system when a failure has occurred at a part of a cache memory, the load due to the I/O processing is clustered to one I/O processing controller and it may result in performance degradation. In addition, when a path switching function to an upper apparatus is not provided, there occurs a problem that an I/O processing can not be taken over.
In addition, the technique described in Patent Document 1 has neither a concept about division of a cache memory into logical memory areas nor a concept of reallocation performed according to a connection state with an upper apparatus and a load status. The technique described in Patent Document 2 also does not have a concept of reallocation of the cache memory according to the connection and access status with an upper apparatus.
In view of these circumstances, an object of the present invention is to solve such a problem as described above and to provide a disk array apparatus where, when a failure has occurred at a part of a cache memory, a memory area of the I/O processing controller except for the memory area where the failure has occurred is utilized without taking over a whole I/O processing to an I/O processing controller of another system so that an influence of performance degradation can be minimized.